Efficient delay test generation for modular circuits

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Date
1996
Authors
Ravikumar, C P
Agrawal, N
Agarwal, P
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Abstract
In this paper, we report a tool called MODET for automatic test generation for path delay faults in modular combinational circuits. Our technique uses precomputed robust delay tests for individual modules to compute robust delay tests for the module-level circuit. We propose a novel technique for path selection in module-level circuits and report efficient algorithms for delay test generation. MODET has been implemented and tested against a number of hierarchical circuits with impressive speedups in relation to gate level test generation
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Keywords
module-level circuit, hierarchical circuits
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